Wireless devices have been in use for many years for enabling mobile communication of voice and data. Such devices can include mobile phones and wireless enabled personal digital assistants (PDA's) for example. Wireless devices are preferably low power to maximize battery life, and small to be packed into progressively shrinking form factor devices. FIG. 1 is a generic block diagram of the core components of such wireless devices. The wireless core 10 includes a base band processor 12 for controlling application specific functions of the wireless device and for providing and receiving voice or data signals to a radio frequency (RF) transceiver chip 14. The RF transceiver chip 14 is responsible for frequency up-conversion of transmission signals, and frequency down-conversion of received signals. RF transceiver chip 14 includes a receiver core 16 connected to an antenna 18 for receiving transmitted signals from a base station or another mobile device, and a transmitter core 20 for transmitting signals through the antenna 18. Those of skill in the art should understand that FIG. 1 is a simplified block diagram, and can include other functional blocks that may be necessary to enable proper operation or functionality.
Generally, the transmitter core 20 is responsible for up-converting electromagnetic signals from base band to higher frequencies for transmission, while receiver core 16 is responsible for down-converting those high frequencies back to their original frequency band when they reach the receiver, processes known as up-conversion and down-conversion (or modulation and demodulation) respectively. The original (or base band) signal, may be, for example, data, voice or video. These base band signals may be produced by transducers such as microphones or video cameras, be computer generated, or transferred from an electronic storage device. In general, the high frequencies provide longer range and higher capacity channels than base band signals, and because high frequency RF signals can propagate through the air, they are preferably used for wireless transmissions as well as hard-wired or fiber channels. All of these signals are generally referred to as RF signals, which are electromagnetic signals; that is, waveforms with electrical and magnetic properties within the electromagnetic spectrum normally associated with radio wave propagation.
FIG. 2 is a schematic representation of a known architecture of the transmitter core 20 as shown in FIG. 1. Such transmitter architecture 50 as seen in FIG. 2 includes a data input for handling a digital signal and an output for producing an analog signal for transmission at an antenna. Accordingly, the transmitter architecture 50 will include both digital and analog circuitry.
Within FIG. 2, data to be transmitted will be digitally modulated with modulator 52 using an in-phase/quadrature (IQ) modulation scheme suitable for the given application. The function of modulator 52 is to provide quadrature I and Q phases of the signal data. This IQ modulation may be Frequency Shift Keyed (FSK), minimum shift keyed (MSK), Gaussian Minimum Shift Keyed (GMSK), Phase Shift Keyed (PSK), Binary Phase Shift Keyed (BPSK), Quadrature Phase Shift Keyed (QPSK), Offset Quadrature Phase Shift Keyed (O-QPSK), or any other suitable digital modulation scheme. For example, a widely used modulation scheme is GMSK within the wireless time division multiple access (TDMA) platform for the Global System for Mobile communications (GSM) standard, whereas the modulation scheme may be QPSK or O-QPSK within the wireless code-division multiple access (CDMA) platform for Interim Standard 95 (IS-95). Once digitally modulated with modulator 52, the sampling rate of the signal is then increased via upsampler 54 to provide a higher bit rate signal. Typically, the modulated data signal is at about 400 KHz and the upsampling increases the data to a higher frequency (e.g., 26 MHz) for further processing. Once upsampled, the data signal is then passed through a reconstruction filter 56 so as to bring the data to the correct values relative to the lower frequency data values.
The reconstructed data signal is then passed to a Digital to Analog Converter (DAC) 58 which represents the point at which the digital architecture passes to an analog architecture. Typically, each element 52 through 58 is driven by a clock signal, clk. It should be understood that the lower frequency digital modulator 52 is clocked via a clock divider 60 where the clock is divided by N, where N is an integer value selected for the given application and desired operating frequencies. The data signal after the DAC 58 is therefore an analog signal. Such analog signal requires filtering due to noise attributed to the DAC 58, which is introduced by the quantization of the signal taking place in the digital-to-analog conversion process in DAC 58. Such filtering is accomplished via 2nd order to 4th order filter 62, and typically consists of a combination of transconductance cells, transconductance-capacitor filters, Metal-Oxide-Silicon-Capacitor (MOS-capacitor) filters, resistor-capacitor (RC) filters, and op-amp circuits arranged in well known configurations. Such a filter 62 serves to reduce the quantization noise from the DAC 58.
The filtered signal is then passed in turn to a voltage to current (V2I) converter 64, a mixer 66, and amplifier/output driver 68 before it is driven onto the antenna. This process beyond the 2nd to 4th order filtering 62 is known as linear direct conversion, or linear upconversion. Essentially, a clock (not shown) is applied at the mixer where the clock frequency is equal to the signal frequency being applied out of the antenna. For example, if the desired antenna signal is to be at 900 MHz, then the clock applied at the mixer will be 900 MHz. Performing such linear upconversion is typically easier using current than using voltage, hence the use of the V2I converter 64. It should be noted that some processing methods involving linear upconversion may involve merely using an inputted analog signal. In such instance, the digital components (i.e., components including DAC and prior), are not required, Regardless, the V2I converter 64 will produce signal distortion because it is a purely analog component. That is to say, when the V2I converter 64 converts voltage to current there will not be precise linear to linear conversion. Rather, there will typically be some level of distortion in such conversion.
At the present time, the aforementioned filtering and V2I conversion components function in the analog domain. This means that they are configured and operated for analog signal processing and can suffer from typical analog circuit problems. For example, the circuit transfer functions can vary between identical circuits on the same chip, and can vary from chip to chip. The varying coefficients of the transfer function will adversely affect its characteristics, such as its phase and pass band shape, for example. Moreover, from a manufacturing cost perspective, analog circuits do not scale well with each process generation. Digital circuits on the other hand are easily scalable. Therefore, mixed circuits will tend to be dominated in size by the analog circuits, unnecessarily increasing the area of the device.
It is, therefore, desirable to provide a wireless transmitter core architecture that will reduce circuit area consumption while maximizing the amount of digital domain circuits to improve signal quality. The use of more digital domain circuits allows for improved scalability while minimizing performance variation due to process variation.